Senior Analog IC Design Engineer
Elevate Semiconductor
San Diego, california
Job Details
Full-time
Full Job Description
Elevate’s mission is to serve our semiconductor and system test customers by providing world class test integrated circuits (ICs) that address the industry’s most complex ATE challenges. We strive to exceed our customer’s expectations, now and well into the future, through designing the lowest power/highest density solutions, with the goal of providing the lowest possible cost of test.
Join our innovative team as a Senior Analog Design Engineer and contribute to the forefront of technology. As a key member of our engineering department, you will play a pivotal role in designing and optimizing analog circuits for our cutting-edge electronic systems.
Responsibilities
- Design and simulate schematics for a diverse range of high-speed and precision CMOS ATE circuits.
- Perform layout, verification, and post-layout simulation for circuits, incorporating Monte Carlo, SOAC, and corner analysis. Conduct mixed-signal simulation at both channel and chip levels.
- Create inventive circuit architectures aimed at optimizing power, performance, and density.
- Conduct IC characterization and provide support for test development and qualification, focusing on ATE-specific parameters and usage conditions.
Requirements
- Bachelor’s degree in electrical engineering; Master's degree preferred.
- 5+ years of professional experience
- Strong foundational knowledge in analog CMOS circuit design.
- Proficiency in designing and analyzing complex feedback loops, including stability analysis and the design of compensation schemes.
- Ability to collaborate seamlessly with internal and external functions such as engineering, manufacturing, and applications to contribute to the development of cutting-edge ATE products.
- Comprehensive understanding of the IC design, qualification, and manufacturing cycle.
- Hands-on experience with industry-standard analog and mixed-signal EDA tools, including but not limited to Cadence, Mentor Graphics, and Tanner. Familiarity with LVS and DRC using Cadence or Mentor tools is essential.